1. Field of the Invention
The present invention relates to a method of and an apparatus for testing the electrostatic breakdown of a semiconductor device and for thereby securely and stably monitoring electrostatic breakdown with use of the charged device model damaged due to electrostatic charges stored on a dielectric package of the semiconductor device.
2. Description of the Prior Art
Conventionally, some methods are known for testing the electrostatic breakdown of a semiconductor device, such as the charged person method assuming the human body model, and the charged device method and the charged package method assuming the charged device model. The electrostatic breakdown on a user side generally occurs on the charged device model because, with the progress of fine semiconductor devices, MOS devices for example have come to have a gate oxide film more reduced in its thickness, and processes of fabricating such a semiconductor device are advanced in their automation.
The charged device model is described with reference to FIG. 1. In the figure, electrostatic charges 15 have been stored on a package surface 14 of a semiconductor device 11. With an input/output terminal 13 being connected to a discharge entity 17, the electrostatic charges are moved from a ground terminal 16 via the discharge entity 17, thereby a discharge current is induced. The induced discharge current damages a semiconductor chip 12.
In the following, a testing method by the charged package method will be described.
As shown in FIG. 2, designated at 1 is a semiconductor device to be tested enclosed in a plastic package, such as a MOS IC device, 2 is a semiconductor chip, 3 is an input/output terminal being an electrode of the semiconductor device 1 external thereto, 4 is a surface of the package, 5 is a metal electrode disposed in contact with the package surface 4, 6 is a DC voltage source for supplying voltage to the metal electrode 5, 7 is a reference potential electrode, 8 is load impedance, 9 is a switch connected between the input/output terminal 3 and the impedance 8, and 10 is package capacitance Cp being the electrostatic capacitance between the semiconductor chip 2 and the metal electrode 5.
In the testing operation, first the switch 9 is opened. Then prescribed voltage is applied to the package surface 4 via the metal electrode 5, with the semiconductor device 1 being insulated from the reference potential electrode 7. In succession, the switch 9 is closed after the lapse of prescribed time, and input/output terminal 3 is electrically connected with the reference potential electrode 7 via the impedance 8, whereby electric charges are stored on the package capacitance Cp 10. With a current forced as such to flow into the semiconductor chip 2 for storing the electric charges on the package capacitance Cp 10, an equivalent phenomenon to the charged device model is produced.
Thereafter, a determination is made as to whether or not the semiconductor device 1 is damaged.
FIG. 3 is an equivalent circuit diagram of the conventional apparatus in FIG. 2. As shown in the FIGURE, the circuit of the MOS IC device 1 is represented by an input protective diode 22, a capacitance Cox 23 of a gate-insulating film of a MOS transistor and input protective resistance RE 24. Designated at 21 is a voltage source terminal. Other elements are given the same numbers as those shown in FIG. 2.
A testing method is often employed which supposes the discharge entity to be metal in general, and hence eliminates the impedance 8 and directly connects electrically between one end of the switch 9 and the reference potential electrode 7. Therefore, the description of the impedance 8 will hereinafter be omitted.
However, upon actual testing of the semiconductor device 1, there is an electrostatic capacitance C.sub.B (hereinafter referred to as back capacitance) between the ground and the power source terminal 21 and an electrostatic capacitance C.sub.I (hereinafter referred to as input/output capacitance) between the ground and the input/output terminal 3, as shown in FIG. 4. Accordingly, even if a prescribed voltage is applied to the package surface 4, the potential of the power source terminal 21 and the input/output terminal 3 varies and hence it is difficult to reliably test the semiconductor device 1.
First, influence of the input/output capacitance C.sub.I will be described.
Upon executing electrostatic breakdown testing for the semiconductor device 1 by use of the charged package method as shown in FIG. 5, the following relation holds between electrostatic capacitance Cair of an air gap existing between a casing piece 30 of a test apparatus and the input/output terminal 3 when the casing piece 30 is present in a confronting relation with the input/output terminal 3: EQU Cair=(.epsilon.o.times..epsilon.s.times.S)/d1 EQU .apprxeq.(8.855.times.10.sup.-14 .times.S)/d1 (1)
Here, .epsilon.o is the vacuum dielectric constant and .epsilon.s is a specific dielectric constant of air which is approximately 1. S is an area of the input/output terminal facing to the casing piece 30, which is represented in cgs units (the same shall be applied hereinafter).
Here, supposing S=2 m/m.times.5 m/m=10.sup.-2 cm.sup.2, the relation between the electrostatic capacitance Cair (fF) and the facing distance d1 (cm) described above is as illustrated in FIG. 6.
Moreover, the electrostatic capacitance Cair corresponds to electrostatic capacitance C.sub.I in an equation (2) described later.
FIG. 7 is an equivalent circuit diagram of the conventional apparatus taking the input/output capacitance C.sub.I into consideration. As shown in the FIGURE, an applied voltage Vcox to the oxide film capacitance Cox 23 when applying prescribed voltage V.sub.1 from the DC voltage source 6 with the switch 9 kept opened is generally expressed as: ##EQU1##
Accordingly, in the example shown in FIG. 5, ##EQU2## holds.
Supposing here that the semiconductor device is a 24 pin-DIP plastic packaged semiconductor device, Cp can be assumed to be 7.1 pF (shown in THE PROCEEDINGS OF IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM 19th, 1981, pp. 193-199). Assuming here that the oxide film capacitance Cox is approximately 0.3 pF, the equation (2) is changed to EQU Vcox.apprxeq.[7.1/(7.4+2405.4d1)].multidot.V.sub.1 (3),
and a relation between the facing distance d1 and the voltage applied to the oxide film capacitance Cox 23 is given as shown in FIG. 8.
Hereupon , forward threshold voltage Vf of the diode 22 of FIG. 7 is assumed 0.5 V.
According to FIG. 8, the diode 22 of FIG. 7 is switched on only by allowing the casing piece 30 of its area S of 2 m/m.times.5 m/m to approach the input/output terminal 3 to about 6 cm therefrom when V.sub.1 =1000 V and to about 3 cm therefrom when V.sub.1 = 500 V. Little transient voltage is applied to the oxide film capacitance Cox 23 even if the switch 9 is closed in the above situation and prevents oxide film breakdown from being produced. It can therefore be confirmed that the electrostatic breakdown voltage of the semiconductor device 1 against the electrostatic breakdown measured on the basis of the charged package method shown in FIG. 7 is sharply varied by the distance between the casing piece 30 and the input/output terminal 3.
The example described above attributed the electrostatic capacitance Cair to the air gap formed between the casing piece 30 and the input/output terminal 3 as the input/output capacitance C.sub.I 26. However, provided the testing is effected on a metallic table, air gap electrostatic capacitance between the table and the input/output terminal 3 also acts as the input/output capacitance C.sub.I. Accordingly, electrostatic breakdown voltage data of the semiconductor device 1 is altered furthermore depending on the shape and size of the table.
The influence of the input/output capacitance C.sub.I will now be described.
As shown in FIG. 9, a metal piece 32 corresponding to part of a casing of the testing apparatus fixed to the ground potential is placed in close vicinity of the package surface 4 at a distance d2 therefrom. The metal piece 32 has an area of 10 mm by 10 mm, for example. Back capacitance C.sub.B exists between the metal piece 32 and the source terminal 21 of the semiconductor device 1.
FIG. 10 shows an equivalent circuit of the testing apparatus taking the back capacitance into consideration. Applied voltage V.sub.s to the voltage source terminal 21 of the semiconductor device 1 satisfies in general: EQU V.sub.s =[Cp/(C.sub.B +Cp)].multidot.V.sub.1 ( 4)
when the DC voltage source 6 is set to prescribed voltage V.sub.1 and the switch 9 is opened.
In equation (4), with the increasing back capacitance C.sub.B, the voltage V.sub.s at the source terminal 21 is reduced. Thereby, when closing the switch 9, voltage Vcox applied to the gate oxide film capacitance Cox of the MOS transistor is lowered after a prescribed time constant to prevent the oxide film from being damaged.
The voltage of the DC power source 6, as the maximum transient voltage is applied to the oxide film capacitor COX 23 after the switch 9 is closed, to thereby damage the oxide film is expressed by: ##EQU3## Here, e is the base of the logarithm, .tau. is the response time of the diode 22, and Vcox(.tau.) is the voltage applied to the oxide film capacitor Cox 23 when the diode 22 responds.
Thereupon, a showing of the relationship between the distance d2 and the breakdown voltage V.sub.B by use of the equation (5) is given in FIG. 11. Here, a 16 pin-DIP type plastic encapsulated semiconductor device is employed for the test and Cp=0.5 pF is assumed. Additionally, Cox=0.3 pF, .tau.=1 nsec, R.sub.E =1000.OMEGA.. The breakdown voltage is 500 V when the back capacitance C.sub.B =0.
As evidenced from FIG. 11, a breakdown voltage V.sub.B of 670 V when the distance d2 is 0.5 cm represents an increase of no less than 34%. Moreover, upon executing the above testing at a distance d2 varying within 1 cm.+-.0.5 cm, the breakdown voltage V.sub.B is altered from 670 V to 550 V even if the same semiconductor device is employed. In fact, it is common that a larger grounding metal piece exists near where the testing in concern is executed, and hence the back capacitance C.sub.B is also increased together with the width of the variation.
Accordingly, upon effecting the electrostatic breakdown testing for the semiconductor device, judgement varies due to the changes of the back capacitance C.sub.B and the input/output capacitance C.sub.I. It is therefore difficult to execute electrostatic breakdown testing of a semiconductor device with good reproducibility and with high reliability.